Lateral diffused metal-oxide-semiconductor (LDMOS) devices are widely used in power management applications for their excellent performance in breakdown voltage BVdss and on-resistance Ron. A conventional LDMOS device may include a well region, and a gate stack including a gate dielectric and a gate electrode over the well region. A body region and a double diffused drain (DDD) region extend to under the gate stack, and are spaced apart by a portion of a well region that is directly under the gate stack. A source pickup region and a drain pickup region are disposed on opposite sides of the gate stack, and are formed over the body region and the DDD region, respectively.
The cell pitch of the LDMOS is determined by the lateral sizes of the gate stack, the body region, the DDD region, and the like. To obtain the desirable breakdown voltage BVdss, the cell pitch of the LDMOS generally cannot be smaller than certain value, and hence on-resistance Ron is sacrificed. Accordingly, the down scaling of the gate density of the LDMOS devices is limited.